Originally Posted by
freexray
I took your comment that generating the carrier on the processor was not feasible as a challenge lol. Got some parts on order to give it a try.
Back of the envelope calculations tell me it is possible (16 instruction per data bit. 8 consumed generating the carrier wave, 8 remain to calculate whether to pin toggle). would be ~1600 instructions of pure sequential code (not a single compare or branch).
Oh, it's definitely do-able, but not on the little PIC. That would take a 40 MHz clock (giving 10 MIPS), which I don't think is available on the smaller PICs, and straight-line code (as you said) where each instruction just twiddles the pins high or low. For a PIC, that's about 800 lines of code (one instruction per carrier edge, or a NOP for no edge).
Unfortunately, the output current of the PIC is still insufficient to drive the tank directly, so we would need to parallel up the output pins, requiring a larger package size. I'd rather just use separate logic gates for their higher drive current, and then the microprocessor can generate just the modulation, which makes the code 1/8 as long and lets the processor run at 1/8 the speed. That's a pretty substantial improvement for an investment of two cheap gates.
But that's only my preference. I'll definitely want to see your experiments!